A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization

This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter compensation technique is proposed in the receiver (RX) to improve timing margins from 0.31 to 0.37 UI at 16 Gb/s, as it adjusts transition slope of the front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation in a PAM-4 signal, relaxed impedance matching is used, where 20 <inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> is used as a transmitter (TX) impedance instead of 50 <inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>. To maximize eye openings further, fractionally spaced feedforward equalization (FS-FFE) is used with a tap spacing of 0.8 UI. The relaxed termination scheme along with FS-FFE improves eye openings by 2.25 times compared with the conventional design using a 50-<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> TX impedance with 1-UI spacing FFE.