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Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion
- Source :
- Circuits and Systems I: Regular Papers, IEEE Transactions on; December 2023, Vol. 70 Issue: 12 p5110-5123, 14p
- Publication Year :
- 2023
-
Abstract
- This paper presents the theory and implementation of a balanced dual-core inverse-class-F (class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula>) voltage-controlled oscillator (VCO). The class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> topology supports high-quality-factor (high-<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula>) differential switched-capacitors (SCs) for both fundamental and 2 <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ nd}}$ </tex-math></inline-formula>-harmonic frequency tuning, which is beneficial for improving the phase noise (PN). However, the unequal parasitic capacitors from the NMOS and PMOS negative <inline-formula> <tex-math notation="LaTeX">${g}$ </tex-math></inline-formula> textsubscript m transistors make it impossible to minimize their flicker noise upconversions simultaneously, especially at high operating frequencies. The mechanism of this effect is analyzed qualitatively with the model of coupled oscillators and verified using the impulse-sensitivity function (ISF) approach. To address this issue, we propose a dual-core class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> VCO that leverages a balanced coupling scheme to minimize the flicker noise upconversions of NMOS and PMOS transistors simultaneously and still keep the advantage of tuning the 2 <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ nd}}$ </tex-math></inline-formula>-harmonic frequency with differential SCs offered by the class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> topology. Additionally, the symmetrical circuit topology aids in improving the differential output balancing. Prototyped in a 28-nm CMOS process without ultra-thick metal, the balanced dual-core class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> VCO dissipates 19.7-mW and achieves a PN of <inline-formula> <tex-math notation="LaTeX">$\!-\!113.9/\!-\!135.8$ </tex-math></inline-formula>-dBc/Hz at 1/10-MHz offset from an 18.23-GHz carrier. Tuned from 15.22 to 18.23-GHz, the proposed VCO exhibits superior figure-of-merits (FoMs) at 1/10-MHz offset from 185.3/187.0 to 186.2/188.1-dBc/Hz.
Details
- Language :
- English
- ISSN :
- 15498328 and 15580806
- Volume :
- 70
- Issue :
- 12
- Database :
- Supplemental Index
- Journal :
- Circuits and Systems I: Regular Papers, IEEE Transactions on
- Publication Type :
- Periodical
- Accession number :
- ejs64986283
- Full Text :
- https://doi.org/10.1109/TCSI.2023.3312817