High-Throughput Nanopore-FET Array Readout IC With 5-MHz Bandwidth and Background Offset/Drift Calibration

This paper presents a high-speed readout interface suitable for nanopore-FET (NPFET) sensor arrays, which are being explored for high-throughput DNA or protein sequencing applications. The readout interface utilises a novel architecture that can simultaneously perform recording and automatic background calibration to compensate for offset and drift of the individual NPFET threshold voltages, eliminating the need for a separate calibration step or an area-consuming DAC. A prototype readout IC has been manufactured in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS to validate the circuit concepts. It features 32 NPFET interface circuits multiplexed to 8 parallel analog outputs. Each individual channel achieves a bandwidth of 10 MHz. The prototype IC has been characterised experimentally, and the online calibration capability has been validated with liquid-gated FETs in a microfluidics setup.