The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor

High-performance large-scale graph analytics are essential to timely analyze relationships in big datasets. Conventional processor architectures suffer from inefficient resource usage and bad scaling on those workloads. To enable efficient and scalable graph analysis, Intel developed the Programmable Integrated Unified Memory Architecture (PIUMA) as a part of the DARPA Hierarchical Identify Verify Exploit (HIVE) program. PIUMA consists of many multithreaded cores, fine-grained memory and network accesses, a globally shared address space, powerful offload engines, and a tightly integrated optical interconnection network. This article presents the PIUMA architecture and documents our experience in designing and building a prototype chip and its bring-up process. PIUMA silicon has successfully powered on demonstrating key aspects of the architecture, some of which will be incorporated into future Intel products.