Improved SOI FinFETs Performance With Low-Temperature Deuterium Annealing

Low-temperature deuterium annealing (LTDA) was applied to a silicon-on-insulator (SOI) n-channel FinFET to improve device performance and reliability. LTDA at 300 °C, which is roughly 100 °C lower than a conventional forming gas annealing (FGA) process with hydrogen, is attractive to reduce the thermal budget. To confirm improved performance, the ON-state current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {on}}{)}$ </tex-math></inline-formula>, OFF-state current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {off}}{)}$ </tex-math></inline-formula>, subthreshold swing (SS), trans-conductance (<inline-formula> <tex-math notation="LaTeX">${g}_{m}{)}$ </tex-math></inline-formula>, and gate leakage current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {G}}{)}$ </tex-math></inline-formula> were evaluated. Thereafter, the parasitic sheet resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{\text {poly,sheet}}$ </tex-math></inline-formula>) of gate was characterized and compared between before and after LTDA. The decreased <inline-formula> <tex-math notation="LaTeX">${R}_{\text {poly,sheet}}$ </tex-math></inline-formula> induced by LTDA is attractive for reducing RC delay. In a reliability point of view, damaged device characteristics by intentional hot-carrier injection (HCI) were recovered by LTDA. In addition to electrical analyses of LTDA effects, deuterium to form the Si–D bonds at the Si channel interface was physically mapped along the perpendicular direction to a FinFET by using time-of-flight secondary-ion mass spectrometry (ToF-SIMS).