ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash Memory

High bit-density flash memories, such as triple-level cell (TLC) and quad-level cell (QLC), have been widely used in flash memory-based storage systems, offering significantly high capacity. However, these high bit-density flash memories suffer from asymmetric access performance on the different pages that sharing the same physical cells. Meanwhile, 3-D flash memory adopts stacking technology to increase capacity and reduce cost per bit. The flash unit can be reprogrammed many times as long as the voltage increases. The reprogramming technology is also an effective solution for further increasing the 3-D flash capacity, allowing multiple program operations in an erase cycle. Considering the restrictions of reprogram operations, solid-state drives (SSDs) should capture the access pattern to perform more reprogramming operations to realize the joint optimization of read and write performance. In this work, we propose an application-specific data allocation and reprogramming technique named ADAR to enhance the read and write performance of 3-D TLC flash memory-based SSDs. The core idea is to allocate low-latency least significant bit (LSB) and central significant bit pages to frequently updated write data (termed hot write data) to improve the write performance, and reprogram the pages from high-latency pages (e.g., most significant bit page) to low-latency pages (e.g., LSB page mode) to enhance the read performance while initially storing frequently read data (termed hot read data) in high-latency pages. We explored data access patterns and designed an effective hotness identification method to present a new data allocation and reprogramming technique for 3-D TLC flash memory. Based on a modified 3-D TLC SSD simulator with typical workloads, our evaluation showed that our technique achieved 35.36% and 25.72% performance improvements in read and write latencies, respectively.