Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>-cubed blue <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>LEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick-and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>LEDs and photosensitive resin. The <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>LEDs arrays with sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%.