Stress Techniques and Mobility Enhancement in FinFET Architectures

Novel device architectures offer improved scalability but come at the price of increased layout sensitivity and reduced effectiveness of stressors. This work focuses on stress effects in n-type FinFETs with gate-first or gate-last stacks, and relies mainly on TCAD results. On n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. CESL becomes very ineffective for layouts with narrow fin pitches with merged fins. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a mobility degradation is predicted. Si:C source/drain stressors are very effective and show similar width dependence as on planar FETs. Significant mobility enhancement is predicted both in isolated and tight-pitch fin configurations.