Deep Levels Induced in Annealed CZ Silicon

The effect of crystalline defects induced in annealed p-type CZ silicon on deep levels has been investigated by transmission electron microscopy and deep level transient spectroscopy. The majority carrier traps, located at Ev+0.47, Ev+ 0.55 and Ev+0.63 eV, have been found in Schottky diodes which contained oxide precipitates (?1011cm-3), dislocation loops (?1010cm-3) and stacking faults (3×109cm-3), respectively. These trap densities are about 1015cm-3. To explain the difference between defect density and trap density, these levels are ascribed to the defect strain. A simple defect strain model is proposed.