Gate Structure Dependence of Variability in Polycrystalline Silicon Fin-Channel Flash Memories

Polycrystalline silicon (poly-Si) fin-channel tri-gate (TG)- and double-gate (DG)-type flash memories with a thin n+-poly-Si floating gate (FG) and different control-gate (CG) lengths ($L_{\text{CG}}$'s) from 76 to 256 nm have been fabricated and their electrical characteristics including statistical threshold voltage ($V_{\text{t}}$) and subthreshold slope ($S$-slope) have been comparatively investigated before and after one program/erase (P/E) cycle. It was experimentally found that better short-channel effect (SCE) immunity, a smaller $V_{\text{t}}$ variation, and a higher program speed are obtained in TG-type flash memories than in DG-type memories. The higher performance of TG-type flash memories is contributed by the additional top gate and recessed bottom silicon dioxide (SiO2) regions, which strengthen the controllability of the channel potential and increase the coupling ratio of the FG to the CG. Therefore, the developed poly-Si fin-channel TG structure is expected to be very useful for the fabrication of high-density and low-cost flash memories.