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Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Authors :
Kamei, Takahiro
Liu, Yongxun
Matsukawa, Takashi
Endo, Kazuhiko
O'uchi, Shinichi
Tsukada, Junichi
Yamauchi, Hiromi
Ishikawa, Yuki
Hayashida, Tetsuro
Sakamoto, Kunihiro
Ogura, Atsushi
Masahara, Meishoku
Source :
Japanese Journal of Applied Physics; June 2012, Vol. 51 Issue: 6 p06FE19-06FE15
Publication Year :
2012

Abstract

Floating-gate (FG)-type tri-gate flash memories with an improved inter-poly dielectric (IPD) layer have been successfully fabricated by introducing a newly developed rapid thermal oxidation (RTO) process, and their NOR-mode operation including threshold voltage ($V_{\text{t}}$) variations before and after one program/erase (P/E) cycle have been systematically investigated. It was experimentally confirmed that the gate breakdown voltage (BV\text{g) is greatly increased from 12 to 19 V by introducing the RTO process thanks to the high quality and thin thermal silicon dioxide (SiO2) formation on the FG surface and etched edge regions, which effectively blocks the leakage pass of the IPD layer. A source--drain (SD) breakdown voltage (BV\text{DS) as high as 4.5 V was obtained even when the gate length ($L_{\text{g}}$) was as small as 117 nm. It was also experimentally confirmed that the memory window increases with increasing gate voltage ($V_{\text{g}}$) in NOR-mode programming thanks to the increased efficiency of channel hot electron (CHE) injection. The developed tri-gate flash memory with improved IPD layer is useful for the further scaling of NOR-type flash memory.

Details

Language :
English
ISSN :
00214922 and 13474065
Volume :
51
Issue :
6
Database :
Supplemental Index
Journal :
Japanese Journal of Applied Physics
Publication Type :
Periodical
Accession number :
ejs27754290
Full Text :
https://doi.org/10.1143/JJAP.51.06FE19