Investigation of Low-Energy Tilted Ion Implantation for Fin-Type Double-Gate Metal--Oxide--Semiconductor Field-Effect Transistor Extension Doping

The low-energy tilted ion implantation (I/I) for fin-type double-gate metal--oxide--semiconductor field-effect transistor (FinFET) source--drain (SD) extension doping is systematically investigated experimentally by fabricating a series of n+-polycrystalline silicon (poly-Si) gate n-channel FinFETs under different I/I conditions. The on-state current ($I_{\text{ON}}$) versus off-state current ($I_{\text{OFF}}$) and the SD parasitic resistance ($R_{\text{p}}$) are used for benchmarking the performance of the fabricated devices to investigate the optimal extension I/I conditions, including dose ($D$) and tilted angle ($\theta$), at a fixed low energy of 5 keV. It is experimentally found that the best extension I/I conditions are $D = 4\times 10^{14}$ cm-2and $\theta = 60$\mbox{\circ}. With further increasing $D$, the device performance deteriorates owing to the incomplete recrystallization of amorphous regions in the thin extension regions. In the case of $\theta = 0$\mbox{\circ}, marked increment and fluctuations in $R_{\text{p}}$ are observed because the implant atoms scatter out randomly from each extension region. The $R_{\text{p}}$ value of the FinFETs fabricated under the above best I/I conditions is comparable to that of devices fabricated by the solid-phase diffusion of phosphors from phosphosilicate glass (PSG). This indicates that the extension I/I conditions of $D = 4\times 10^{14}$ cm-2and $\theta = 60$\mbox{\circ} are almost optimal and is very effective for high-performance FinFET fabrication.