What is ECO for high-level synthesis?

Functional verification at the Register Transfer Level is quite often the most time and resource consuming step of the entire design flow of a digital integrated circuit. For this reason, designers are moving towards high-level design methods in which they explore different algorithmic approaches, change memory organization, and modify area, power and performance constraints, in order to delimit the trade-off space and select points worthy of deeper investigation. During these phases, functional verifications are carried out continuously using fast simulation models in C, C++ or SystemC, in order to ensure that the design is correct with respect to its specifications. The result is a "golden" RTL specification that becomes very expensive to modify once the following logical and physical design steps have started, because executing functional verification is very time consuming. Moreover, any significant changes to the logic circuit are extremely risky, since the physical design steps may no longer satisfy performance constraints, and lengthy iterations are required to properly re-constrain the implementation.