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FoCs - Automatic Generation of Simulation Checkers from Formal Specifications.

Authors :
Emerson, E. Allen
Sistla, A. Prasad
Abarbanel, Yael
Beer, Ilan
Gluhovsky, Leonid
Keidar, Sharon
Wolfsthal, Yaron
Source :
Computer Aided Verification; 2000, p538-542, 5p
Publication Year :
2000

Abstract

For the foreseeable future, industrial hardware design will continue to use both simulation and model checking in the design verification process. To date, these techniques are applied in isolation using different tools and methodologies, and different formulations of the problem. This results in cumulative high cost and little (if any) cross-leverage of the individual advantages of simulation and formal verification. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISBNs :
9783540677703
Database :
Supplemental Index
Journal :
Computer Aided Verification
Publication Type :
Book
Accession number :
32865785
Full Text :
https://doi.org/10.1007/10722167_40