Novel Design of a Digital PLL for Power Reduction.

Very large-scale integration (VLSI) circuits operating at ultra-low power are currently acquiring more attention from the research group and the industries too. The energy efficient sensor nodes with reduced size are much preferred among applications such as wireless sensor networks, pollution and plant monitoring. The biggest challenge faced by the VLSI designers in present day life is designing a product of new generation which operates on minimum possible power. As an operational gadget, the PLL has wide scope of utilization in media transmission, PCs and electronic applications for jitter reduction, clock synthesis, synchronization etc. As a result, a PLL that can function in the GHz range while consuming less power is required. In this paper, designing and analysis of PLL with numerous outputs has been proposed to be implemented by changing the closed loop frequency control framework PLL blocks. As such, highly effective, low power, ideal area chip can be used for PLL with four various yields as PLL 8x, PLL 4x, PLL 2x and PLL 1x with different frequencies separately. Likewise, it is planned to utilize multi-threshold technique to minimize the leakage current in the circuit. Further, the performance verification of various parameters of PLL are done to acquire negligible power. Direct toolbox YALMIP is used as programming solver as an optimization tool. In addition to this, another method of non-dominated sorting genetic algorithm (NSGA-II) Correlation for optimization is also introduced between both the strategies to find the best outcomes. [ABSTRACT FROM AUTHOR]