Low‐ripple coarse‐fine digital low‐dropout regulator without ringing in the transient state.

Herein, a low‐ripple coarse‐fine digital low‐dropout regulator (D‐LDO) without ringing in the transient state is proposed. Conventional D‐LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D‐LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D‐LDO was fabricated using a 65‐nm CMOS process with an area of 0.0056 μm2. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 μs to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 μA. [ABSTRACT FROM AUTHOR]