Back to Search Start Over

Serial interfaces tax even best-laid test plan.

Authors :
Wilson, Ron
Source :
Communication Systems Design; Sep2003, Vol. 9 Issue 9, p28, 2/3p
Publication Year :
2003

Abstract

Focuses on the high-speed serial interfaces on system-level chips. Implication of the interface for the chip's production test plan; Kind of testing and characterization of the interface; Problem of the interface in serial lines.

Details

Language :
English
ISSN :
10864644
Volume :
9
Issue :
9
Database :
Supplemental Index
Journal :
Communication Systems Design
Publication Type :
Periodical
Accession number :
10877137