Back to Search Start Over

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.

Authors :
Hao Li
Shuai Chen
Liqiong Yang
Rui Bai
Weiwu Hu
Zhong, Freeman Y.
Palermo, Samuel
Chiang, Patrick Yin
Source :
2014 Symposium on VLSI Circuits Digest of Technical Papers; 2014, p1-2, 2p
Publication Year :
2014

Details

Language :
English
ISBNs :
9781479933273
Database :
Complementary Index
Journal :
2014 Symposium on VLSI Circuits Digest of Technical Papers
Publication Type :
Conference
Accession number :
98464177
Full Text :
https://doi.org/10.1109/VLSIC.2014.6858399