Active Mode Subclock Power Gating.

MLA

Mistry, Jatin N., et al. “Active Mode Subclock Power Gating.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 9, Sept. 2014, pp. 1898–908. EBSCOhost, https://doi.org/10.1109/TVLSI.2013.2280886.

APA

Mistry, J. N., Myers, J., Al-Hashimi, B. M., Flynn, D., Biggs, J., & Merrett, G. V. (2014). Active Mode Subclock Power Gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(9), 1898–1908. https://doi.org/10.1109/TVLSI.2013.2280886

Chicago

Mistry, Jatin N., James Myers, Bashir M. Al-Hashimi, David Flynn, John Biggs, and Geoff V. Merrett. 2014. “Active Mode Subclock Power Gating.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (9): 1898–1908. doi:10.1109/TVLSI.2013.2280886.