6.1 memory and system architecture for 400Gb/s networking and beyond.

MLA

Maheshwari, Dinesh. “6.1 Memory and System Architecture for 400Gb/s Networking and Beyond.” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Jan. 2014, pp. 116–17. EBSCOhost, https://doi.org/10.1109/ISSCC.2014.6757362.

APA

Maheshwari, D. (2014). 6.1 memory and system architecture for 400Gb/s networking and beyond. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 116–117. https://doi.org/10.1109/ISSCC.2014.6757362

Chicago

Maheshwari, Dinesh. 2014. “6.1 Memory and System Architecture for 400Gb/s Networking and Beyond.” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), January, 116–17. doi:10.1109/ISSCC.2014.6757362.