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Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds.

Authors :
Hanamura, S.
Aoki, M.
Masuhara, T.
Minato, O.
Sakai, Y.
Hayashida, T.
Source :
IEEE Transactions on Electron Devices; 1987, Vol. 34 Issue 1, p94-100, 7p
Publication Year :
1987

Details

Language :
English
ISSN :
00189383
Volume :
34
Issue :
1
Database :
Complementary Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
93116058
Full Text :
https://doi.org/10.1109/T-ED.1987.22890