A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure.

MLA

Aoki, M., et al. “A 60-Ns 16-Mbit CMOS DRAM with a Transposed Data-Line Structure.” IEEE Journal of Solid-State Circuits, vol. 23, no. 5, Jan. 1988, pp. 1113–19. EBSCOhost, https://doi.org/10.1109/4.5932.

APA

Aoki, M., Nakagome, Y., Horiguchi, M., Tanaka, H., Ikenaga, S., Etoh, J., Kawamoto, Y., Kimura, S., Takeda, E., Sunami, H., & Itoh, K. (1988). A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure. IEEE Journal of Solid-State Circuits, 23(5), 1113–1119. https://doi.org/10.1109/4.5932

Chicago

Aoki, M., Y. Nakagome, M. Horiguchi, H. Tanaka, S. Ikenaga, J. Etoh, Y. Kawamoto, et al. 1988. “A 60-Ns 16-Mbit CMOS DRAM with a Transposed Data-Line Structure.” IEEE Journal of Solid-State Circuits 23 (5): 1113–19. doi:10.1109/4.5932.