A 4K CMOS gate array with automatically generated test circuits.

MLA

Kuboki, S., et al. “A 4K CMOS Gate Array with Automatically Generated Test Circuits.” IEEE Journal of Solid-State Circuits, vol. 20, no. 5, Jan. 1985, pp. 1018–24. EBSCOhost, https://doi.org/10.1109/JSSC.1985.1052430.

APA

Kuboki, S., Masuda, I., Hayashi, T., & Torii, S. (1985). A 4K CMOS gate array with automatically generated test circuits. IEEE Journal of Solid-State Circuits, 20(5), 1018–1024. https://doi.org/10.1109/JSSC.1985.1052430

Chicago

Kuboki, S., I. Masuda, T. Hayashi, and S. Torii. 1985. “A 4K CMOS Gate Array with Automatically Generated Test Circuits.” IEEE Journal of Solid-State Circuits 20 (5): 1018–24. doi:10.1109/JSSC.1985.1052430.