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A 256K CMOS SRAM with variable impedance data-line loads.

Authors :
Yamamoto, S.
Tanimura, N.
Nagasawa, K.
Meguro, S.
Yasui, T.
Minato, O.
Masuhara, T.
Source :
IEEE Journal of Solid-State Circuits; 1985, Vol. 20 Issue 5, p924-928, 5p
Publication Year :
1985

Details

Language :
English
ISSN :
00189200
Volume :
20
Issue :
5
Database :
Complementary Index
Journal :
IEEE Journal of Solid-State Circuits
Publication Type :
Academic Journal
Accession number :
92811392
Full Text :
https://doi.org/10.1109/JSSC.1985.1052416