A 32-bank 256 Mb DRAM with cache and TAG.

Authors :: Tanoi, S.
Tanaka, Y.
Tanabe, T.
Kita, A.
Inada, T.
Hamazaki, R.
Ohtsuki, Y.
Uesugi, M.
Source :: Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94; 1994, p144-145, 2p
Publication Year :: 1994

Language :: English
ISBNs :: 9780780318441
Database :: Complementary Index
Journal :: Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94
Publication Type :: Conference
Accession number :: 92489646
Full Text :: https://doi.org/10.1109/ISSCC.1994.344695