A 25 ns 4 Mb CMOS SRAM with dynamic bit line loads.

Authors :: Miyaji, F.
Matsuyama, Y.
Naiki, I.
Takahashi, H.
Sasaki, M.
Takeda, M.
Sugano, Y.
Hagiwara, Y.
Nishiyama, K.
Tsumori, T.
Kobayashi, K.
Hirano, K.
Shimada, T.
Source :: IEEE International Solid-State Circuits Conference, 1989 ISSCC Digest of Technical Papers; 1989, p250-251, 2p
Publication Year :: 1989

Language :: English
Database :: Complementary Index
Journal :: IEEE International Solid-State Circuits Conference, 1989 ISSCC Digest of Technical Papers
Publication Type :: Conference
Accession number :: 92479876
Full Text :: https://doi.org/10.1109/ISSCC.1989.48277