A 50 MIPS (peak) 32/64 b microprocessor.

Authors :: Conrad, R.
Devlin, R.
Dobberpuhl, D.
Gieseke, B.
Heye, R.
Hoeppner, G.
Kowaleski, J.
Ladd, M.
Montanaro, J.
Morris, S.
Stamm, R.
Tumblin, H.
Witek, R.
Source :: IEEE International Solid-State Circuits Conference, 1989 ISSCC Digest of Technical Papers; 1989, p76-77, 2p
Publication Year :: 1989

Language :: English
Database :: Complementary Index
Journal :: IEEE International Solid-State Circuits Conference, 1989 ISSCC Digest of Technical Papers
Publication Type :: Conference
Accession number :: 92479788
Full Text :: https://doi.org/10.1109/ISSCC.1989.48185