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Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks.

Authors :
Bombana, M.
Buonanno, G.
Cavalloro, P.
Ferrandi, F.
Sciuto, D.
Zaza, G.
Source :
Proceedings of 1993 IEEE International Workshop on Defect & Fault Tolerance in VLSI Systems; 1993, p223-230, 8p
Publication Year :
1993

Details

Language :
English
ISBNs :
9780818635021
Database :
Complementary Index
Journal :
Proceedings of 1993 IEEE International Workshop on Defect & Fault Tolerance in VLSI Systems
Publication Type :
Conference
Accession number :
92260839
Full Text :
https://doi.org/10.1109/DFTVS.1993.595805