Cite
Efficient path selection for delay testing based on partial path evaluation.
MLA
Tani, S., et al. “Efficient Path Selection for Delay Testing Based on Partial Path Evaluation.” Proceedings 16th IEEE VLSI Test Symposium (Cat No98TB100231), Jan. 1998, pp. 188–93. EBSCOhost, https://doi.org/10.1109/VTEST.1998.670867.
APA
Tani, S., Teramoto, M., Fukazawa, T., & Matsuhiro, K. (1998). Efficient path selection for delay testing based on partial path evaluation. Proceedings 16th IEEE VLSI Test Symposium (Cat No98TB100231), 188–193. https://doi.org/10.1109/VTEST.1998.670867
Chicago
Tani, S., M. Teramoto, T. Fukazawa, and K. Matsuhiro. 1998. “Efficient Path Selection for Delay Testing Based on Partial Path Evaluation.” Proceedings 16th IEEE VLSI Test Symposium (Cat No98TB100231), January, 188–93. doi:10.1109/VTEST.1998.670867.