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A 500 MHz 4 Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O.
- Source :
- 1997 IEEE International Solids-State Circuits Conference Digest of Technical Papers; 1997, p406-407, 2p
- Publication Year :
- 1997
Details
- Language :
- English
- ISBNs :
- 9780780337213
- Database :
- Complementary Index
- Journal :
- 1997 IEEE International Solids-State Circuits Conference Digest of Technical Papers
- Publication Type :
- Conference
- Accession number :
- 92119670
- Full Text :
- https://doi.org/10.1109/ISSCC.1997.585461