A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.

MLA

Chen, Ming-Pin, et al. “A 260mV L-Shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.” 2012 Symposium on VLSI Circuits (VLSIC), Jan. 2012, pp. 112–13. EBSCOhost, https://doi.org/10.1109/VLSIC.2012.6243815.

APA

Chen, M.-P., Chen, L.-F., Chang, M.-F., Yang, S.-M., Kuo, Y.-J., Wu, J.-J., Ho, M.-S., Su, H.-Y., Chu, Y.-H., Wu, W.-C., Yang, T.-Y., & Yamauchi, H. (2012). A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. 2012 Symposium on VLSI Circuits (VLSIC), 112–113. https://doi.org/10.1109/VLSIC.2012.6243815

Chicago

Chen, Ming-Pin, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, et al. 2012. “A 260mV L-Shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.” 2012 Symposium on VLSI Circuits (VLSIC), January, 112–13. doi:10.1109/VLSIC.2012.6243815.