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A comparison of two approaches to multi-operand binary addition.
- Source :
- 1978 IEEE 4th Symposium Computer Arithmetic (ARITH); 1/ 1/1978, p125-139, 15p
- Publication Year :
- 1978
-
Abstract
- This paper presents the results of one phase of a study concerning methods for addition of P>2 numbers, each encoded as a vector of digits (digit vector) of length N. Such multi-operand addition has been studied most often in the context of reducing a set of partial products to a single result in the implementation of multiplication. More generalized multi-operand addition, most notably in the form of inner product calculations is, however, central to numerous scientific applications of digital computers. Although multi-operand addition is trivially accomplished by accumulation (iteration in time) in any general purpose machine, demands for very high-speed computation, typified by 2- and 3-D signal processing prompt implementation of dedicated, hardware-intensive structures for multi-operand addition. This study, for example, is motivated in part by requirements for rapid simultaneous addition of up to 100, 16-bit operands in the design of a dedicated processor for real-time reconstruction of 3-D images of the beating heart and breathing lungs [1]. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- Database :
- Complementary Index
- Journal :
- 1978 IEEE 4th Symposium Computer Arithmetic (ARITH)
- Publication Type :
- Conference
- Accession number :
- 86471163
- Full Text :
- https://doi.org/10.1109/ARITH.1978.6155765