Cite

An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication.

MLA

Warner, K., et al. “An Investigation of Wafer-to-Wafer Alignment Tolerances for Three-Dimensional Integrated Circuit Fabrication.” 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), Jan. 2004, pp. 71–72. EBSCOhost, https://doi.org/10.1109/SOI.2004.1391560.



APA

Warner, K., Chen, C., D’Onofrio, R., Keast, C., & Poesse, S. (2004). An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication. 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 71–72. https://doi.org/10.1109/SOI.2004.1391560



Chicago

Warner, K., C. Chen, R. D’Onofrio, C. Keast, and S. Poesse. 2004. “An Investigation of Wafer-to-Wafer Alignment Tolerances for Three-Dimensional Integrated Circuit Fabrication.” 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), January, 71–72. doi:10.1109/SOI.2004.1391560.