Cite
Exploiting VHDL-RTL features to reduce the complexity of power estimation in combinational circuits.
MLA
Machado, F., et al. “Exploiting VHDL-RTL Features to Reduce the Complexity of Power Estimation in Combinational Circuits.” 2005 PhD Research in Microelectronics & Electronics, Jan. 2005, pp. 111–14. EBSCOhost, https://doi.org/10.1109/RME.2005.1542949.
APA
Machado, F., Torroja, Y., & Riesgo, T. (2005). Exploiting VHDL-RTL features to reduce the complexity of power estimation in combinational circuits. 2005 PhD Research in Microelectronics & Electronics, 111–114. https://doi.org/10.1109/RME.2005.1542949
Chicago
Machado, F., Y. Torroja, and T. Riesgo. 2005. “Exploiting VHDL-RTL Features to Reduce the Complexity of Power Estimation in Combinational Circuits.” 2005 PhD Research in Microelectronics & Electronics, January, 111–14. doi:10.1109/RME.2005.1542949.