Cite

The development of a hardware abstraction layer generator for system-on-chip functional verification.

MLA

Lins, T., and E. Barros. “The Development of a Hardware Abstraction Layer Generator for System-on-Chip Functional Verification.” 2010 VI Southern Programmable Logic Conference (SPL), Jan. 2010, pp. 41–46. EBSCOhost, https://doi.org/10.1109/SPL.2010.5483004.



APA

Lins, T., & Barros, E. (2010). The development of a hardware abstraction layer generator for system-on-chip functional verification. 2010 VI Southern Programmable Logic Conference (SPL), 41–46. https://doi.org/10.1109/SPL.2010.5483004



Chicago

Lins, T., and E. Barros. 2010. “The Development of a Hardware Abstraction Layer Generator for System-on-Chip Functional Verification.” 2010 VI Southern Programmable Logic Conference (SPL), January, 41–46. doi:10.1109/SPL.2010.5483004.