Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC™ instruction set architecture.

Details

Language :

English

ISBNs :

9780769515700

Database :

Complementary Index

Journal :

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

Publication Type :

Conference

Accession number :

81648230

Full Text :

https://doi.org/10.1109/VTS.2002.1011103