A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography.

MLA

Nackaerts, A., et al. “A 0.314μm2 6T-SRAM Cell Build with Tall Triple-Gate Devices for 45nm Applications Using 0.75NA 193nm Lithography.” IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, Jan. 2004, pp. 269–72. EBSCOhost, https://doi.org/10.1109/IEDM.2004.1419129.

APA

Nackaerts, A., Ercken, M., Demuynck, S., Lauwers, A., Baerts, C., Bender, H., Boulaert, W., Collaert, N., Degroote, B., Delvaux, C., de Marneffe, J. F., Dixit, A., De Meyer, K., Hendrickx, E., Heylen, N., Jaenen, P., Laidler, D., Locorotondo, S., Maenhoudt, M., & Moelants, M. (2004). A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography. IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 269–272. https://doi.org/10.1109/IEDM.2004.1419129

Chicago

Nackaerts, A., M. Ercken, S. Demuynck, A. Lauwers, C. Baerts, H. Bender, W. Boulaert, et al. 2004. “A 0.314μm2 6T-SRAM Cell Build with Tall Triple-Gate Devices for 45nm Applications Using 0.75NA 193nm Lithography.” IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, January, 269–72. doi:10.1109/IEDM.2004.1419129.