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A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography.

Authors :
Nackaerts, A.
Ercken, M.
Demuynck, S.
Lauwers, A.
Baerts, C.
Bender, H.
Boulaert, W.
Collaert, N.
Degroote, B.
Delvaux, C.
de Marneffe, J.F.
Dixit, A.
De Meyer, K.
Hendrickx, E.
Heylen, N.
Jaenen, P.
Laidler, D.
Locorotondo, S.
Maenhoudt, M.
Moelants, M.
Source :
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004; 2004, p269-272, 4p
Publication Year :
2004

Details

Language :
English
ISBNs :
9780780386846
Database :
Complementary Index
Journal :
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004
Publication Type :
Conference
Accession number :
81609661
Full Text :
https://doi.org/10.1109/IEDM.2004.1419129
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