Advanced ESD power clamp design for SOI FinFET CMOS technology.

MLA

Thijs, S., et al. “Advanced ESD Power Clamp Design for SOI FinFET CMOS Technology.” 2010 IEEE International Conference on IC Design & Technology (ICICDT), Jan. 2010, pp. 43–46. EBSCOhost, https://doi.org/10.1109/ICICDT.2010.5510299.

APA

Thijs, S., Tre, mouilles, D., Linten, D., Iyer, N. M., Griffoni, A., & Groeseneken, G. (2010). Advanced ESD power clamp design for SOI FinFET CMOS technology. 2010 IEEE International Conference on IC Design & Technology (ICICDT), 43–46. https://doi.org/10.1109/ICICDT.2010.5510299

Chicago

Thijs, S., mouilles, D. Tre, D. Linten, N.M. Iyer, A. Griffoni, and G. Groeseneken. 2010. “Advanced ESD Power Clamp Design for SOI FinFET CMOS Technology.” 2010 IEEE International Conference on IC Design & Technology (ICICDT), January, 43–46. doi:10.1109/ICICDT.2010.5510299.