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Scan-architecture-based evaluation technique of SET and SEU soft-error rates at each flip-flop in logic VLSI systems.

Authors :
Yanagawa, Y.
Kobayashi, D.
Ikeda, H.
Saito, H.
Hirose, K.
Source :
2007 9th European Conference on Radiation & Its Effects on Components & Systems; 2007, p1-6, 6p
Publication Year :
2007

Details

Language :
English
ISBNs :
9781424417049
Database :
Complementary Index
Journal :
2007 9th European Conference on Radiation & Its Effects on Components & Systems
Publication Type :
Conference
Accession number :
81360410
Full Text :
https://doi.org/10.1109/RADECS.2007.5205569