A fast low-power modulo 2n+1 multiplier design.

MLA

Modugu, R., et al. “A Fast Low-Power modulo 2n+1 Multiplier Design.” 2009 IEEE Instrumentation & Measurement Technology Conference, Jan. 2009, pp. 951–56. EBSCOhost, https://doi.org/10.1109/IMTC.2009.5168589.

APA

Modugu, R., Minsu Choi, & Park, N. (2009). A fast low-power modulo 2n+1 multiplier design. 2009 IEEE Instrumentation & Measurement Technology Conference, 951–956. https://doi.org/10.1109/IMTC.2009.5168589

Chicago

Modugu, R., Minsu Choi, and N. Park. 2009. “A Fast Low-Power modulo 2n+1 Multiplier Design.” 2009 IEEE Instrumentation & Measurement Technology Conference, January, 951–56. doi:10.1109/IMTC.2009.5168589.