A high speed Reed–Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm.

MLA

Hsie-Chia Chang, et al. “A High Speed Reed–Solomon Decoder Chip Using Inversionless Decomposed Architecture for Euclidean Algorithm.” Proceedings of the 28th European Solid-State Circuits Conference, Jan. 2002, pp. 519–22. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edb&AN=81238253&authtype=sso&custid=ns315887.

APA

Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, & Chen-Yi Lee. (2002). A high speed Reed–Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm. Proceedings of the 28th European Solid-State Circuits Conference, 519–522.

Chicago

Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, and Chen-Yi Lee. 2002. “A High Speed Reed–Solomon Decoder Chip Using Inversionless Decomposed Architecture for Euclidean Algorithm.” Proceedings of the 28th European Solid-State Circuits Conference, January, 519–22. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edb&AN=81238253&authtype=sso&custid=ns315887.