A 15 MHz – 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS.

MLA

Hoyos, S., et al. “A 15 MHz – 600 MHz, 20 MW, 0.38 Mm2, Fast Coarse Locking Digital DLL in 0.13μm CMOS.” ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Jan. 2008, pp. 90–93. EBSCOhost, https://doi.org/10.1109/ESSCIRC.2008.4681799.

APA

Hoyos, S., Tsang, C. W., Vanderhaegen, J., Chiu, Y., Aibara, Y., Khorramabadi, H., & Nikolic, B. (2008). A 15 MHz – 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 90–93. https://doi.org/10.1109/ESSCIRC.2008.4681799

Chicago

Hoyos, S., C.W. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, and B. Nikolic. 2008. “A 15 MHz – 600 MHz, 20 MW, 0.38 Mm2, Fast Coarse Locking Digital DLL in 0.13μm CMOS.” ESSCIRC 2008 - 34th European Solid-State Circuits Conference, January, 90–93. doi:10.1109/ESSCIRC.2008.4681799.