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An accurate gate delay model for high speed digital and analog circuits.
- Source :
- 2008 IEEE Dallas Circuits & Systems Workshop: System-on-Chip - Design, Applications, Integration & Software; 2008, p1-4, 4p
- Publication Year :
- 2008
Details
- Language :
- English
- ISBNs :
- 9781424429554
- Database :
- Complementary Index
- Journal :
- 2008 IEEE Dallas Circuits & Systems Workshop: System-on-Chip - Design, Applications, Integration & Software
- Publication Type :
- Conference
- Accession number :
- 81008119
- Full Text :
- https://doi.org/10.1109/DCAS.2008.4695915