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A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.

Authors :
Harwood, M.
Warke, N.
Simpson, R.
Leslie, T.
Amerasekera, A.
Batty, S.
Colman, D.
Carr, E.
Gopinathan, V.
Hubbins, S.
Hunt, P.
Joy, A.
Khandelwal, P.
Killips, B.
Krause, T.
Lytollis, S.
Pickering, A.
Saxton, M.
Sebastio, D.
Swanson, G.
Source :
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers; 2007, p436-591, 156p
Publication Year :
2007

Details

Language :
English
ISBNs :
9781424408535
Database :
Complementary Index
Journal :
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
Publication Type :
Conference
Accession number :
80912160
Full Text :
https://doi.org/10.1109/ISSCC.2007.373481
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