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A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell.

Authors :
Kuan-Lun Cheng
Wu, C.C.
Wang, Y.P.
Lin, D.W.
Chu, C.M.
Tarng, Y.Y.
Lu, S.Y.
Yang, S.J.
Hsieh, M.H.
Liu, C.M.
Fu, S.P.
Chen, J.H.
Lin, C.T.
Lien, W.Y.
Huang, H.Y.
Wang, P.W.
Lin, H.H.
Lee, D.Y.
Huang, M.J.
Nieh, C.F.
Source :
2007 IEEE International Electron Devices Meeting; 2007, p243-246, 4p
Publication Year :
2007

Details

Language :
English
ISBNs :
9781424415083
Database :
Complementary Index
Journal :
2007 IEEE International Electron Devices Meeting
Publication Type :
Conference
Accession number :
80908596
Full Text :
https://doi.org/10.1109/IEDM.2007.4418913
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