Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 μm DRAMs and beyond.

MLA

Sato, M., et al. “Transistor on Capacitor (TOC) Cell with Quarter Pitch Layout for 0.13 Μm DRAMs and Beyond.” 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), Jan. 2000, pp. 82–83. EBSCOhost, https://doi.org/10.1109/VLSIT.2000.852778.

APA

Sato, M., Ishibashi, S., Kajiyama, T., Sakuma, M., Mizushima, I., Tsunashima, Y., Shoji, F., Yano, H., Nitayama, A., & Hamamoto, T. (2000). Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 μm DRAMs and beyond. 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 82–83. https://doi.org/10.1109/VLSIT.2000.852778

Chicago

Sato, M., S. Ishibashi, T. Kajiyama, M. Sakuma, I. Mizushima, Y. Tsunashima, F. Shoji, H. Yano, A. Nitayama, and T. Hamamoto. 2000. “Transistor on Capacitor (TOC) Cell with Quarter Pitch Layout for 0.13 Μm DRAMs and Beyond.” 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), January, 82–83. doi:10.1109/VLSIT.2000.852778.