Line Edge Roughness (LER) correlation and dielectric reliability with Spacer-Defined Double Patterning (SDDP) at 20nm half pitch.

MLA

Yong Kong Siew, et al. “Line Edge Roughness (LER) Correlation and Dielectric Reliability with Spacer-Defined Double Patterning (SDDP) at 20nm Half Pitch.” Interconnect Technology Conference & 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International, Jan. 2011, pp. 1–3. EBSCOhost, https://doi.org/10.1109/IITC.2011.5940296.

APA

Yong Kong Siew, Stucchi, M., Versluijs, J., Roussel, P., Kunnen, E., Pantouvaki, M., Beyer, G. P., & Tokei, Z. (2011). Line Edge Roughness (LER) correlation and dielectric reliability with Spacer-Defined Double Patterning (SDDP) at 20nm half pitch. Interconnect Technology Conference & 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International, 1–3. https://doi.org/10.1109/IITC.2011.5940296

Chicago

Yong Kong Siew, M. Stucchi, J. Versluijs, P. Roussel, E. Kunnen, M. Pantouvaki, G.P. Beyer, and Z. Tokei. 2011. “Line Edge Roughness (LER) Correlation and Dielectric Reliability with Spacer-Defined Double Patterning (SDDP) at 20nm Half Pitch.” Interconnect Technology Conference & 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International, January, 1–3. doi:10.1109/IITC.2011.5940296.