Multi Vt 7T SRAM cell for high speed application at 45 nm technology.

The trend of decreasing device size and increasing chip densities involving several hundred millions of transistors per chip has resulted in tremendous increase in design complexity. Low power SRAMs are essential in today's demand as they are preferred as on chip memories with read write stability. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. The proposed seven-transistor SRAM cell for very high density and low power embedded applications as well as for stand-alone SRAM applications. It uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell. This paper presents a method based on multi-Vt to increase read, write stability and reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and it is also depend on Vt. The Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results obtained for this paper. [ABSTRACT FROM AUTHOR]