A low cost hierarchical system for VLSI layout and verification.

MLA

Edmondson, Tom H., and Richard M. Jennings. “A Low Cost Hierarchical System for VLSI Layout and Verification.” DAC: Annual ACM/IEEE Design Automation Conference, June 1981, pp. 505–10. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edb&AN=73580929&authtype=sso&custid=ns315887.

APA

Edmondson, T. H., & Jennings, R. M. (1981). A low cost hierarchical system for VLSI layout and verification. DAC: Annual ACM/IEEE Design Automation Conference, 505–510.

Chicago

Edmondson, Tom H., and Richard M. Jennings. 1981. “A Low Cost Hierarchical System for VLSI Layout and Verification.” DAC: Annual ACM/IEEE Design Automation Conference, June, 505–10. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edb&AN=73580929&authtype=sso&custid=ns315887.